1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including contact pins and a method of manufacturing the same.
2. Description of the Related Art
Memory cards may be widely used in electronic devices (e.g., multimedia devices, such as digital cameras and MP3 players). A memory card may include a given surface with a contact pin array for providing an electrical connection (e.g., with an associated electronic device). Accordingly, a user of the memory card may need to align the memory card in a proper orientation the memory card into a device's memory slot.
FIG. 1(a) illustrates a front surface of a conventional memory card 100. FIG. 1(b) illustrates a rear surface of the conventional memory card 100. Referring to FIGS. 1(a) and 1(b), a contact pin array 105 may be formed on the rear surface of the conventional memory card 100 as shown in FIG. 1(b). The front surface of the conventional memory card 100 may not include a contact pin array.
FIG. 2 illustrates an insertion of the memory card 100 into a memory slot 108 of a digital camera 110. Referring to FIG. 2, if the front surface of the memory card 100 faces upward (e.g., with respect to the digital camera 110), the memory card 100 may fit into the memory slot 108 and may connect to the digital camera 110 (e.g., because the contact pin array 105 may be aligned with the memory slot 108). However, if the rear surface of the memory card 100, as illustrated in FIG. 1(b), faces upward (e.g., with respect to the digital camera 110), the memory card 100 may neither fit into the memory slot 108 nor connect to the digital camera 110, as will be described in greater detail below with reference to FIG.3.
FIG. 3 illustrates an improper insertion of the memory card 100 into the memory slot 108 of the digital camera 110. Unlike the insertion illustrated in FIG. 2, in FIG. 3 the memory card 100 may not fit properly into the memory slot 108 of the digital camera 110 (e.g., because the contact pin array 105 may not be aligned with the memory slot 108). As shown in FIG. 3, if the memory card 100 is forced into the memory slot 108 (e.g., without a proper fit), the memory card 100 and/or the digital camera 110 may be damaged. Further, the memory slot 108 may also be damaged.
FIG. 4(a) illustrates the contact pin array 105 of the memory card 100. Referring to FIG. 4(a), the contact pin array 105 may include contact pins 1 through 9 which may be formed on a given surface or side of the memory card 100 (e.g., for example, on a rear surface).
FIG. 4(b) illustrates attributes of the contact pins 1 through 9 of the contact pin array 105 of FIG. 4(a). Referring to FIG. 4(b), the attributes may include a name, a type and a function associated with each of the contact pins 1 through 9. For example, contact pins 1, 7, 8, and 9 may be used as data lines for data transfers to/from the memory device 100.
During an operation where data may be read from the memory card 100, a command (e.g., a read command) may be received by the memory card 100 through contact pin 2 (e.g., for transferring commands to and from the memory card 100) and the memory card 100 may respond to the command (e.g., with an acknowledgment, the requested data, etc.). Data blocks may be output through contact pins 1, 7, 8, and 9, each of which may be designated as data lines. Assuming that the length of a given data block is 8 bits, a transmission of the given data block using the four contact pins 1, 7, 8, and 9 may require at least two clock signals.
FIG. 5(a) illustrates a conventional data block transmission structure. Referring to FIG. 5(a), if a data block is read using a single data line, for example DAT0 (e.g., which may correspond to one of contact pins 1 through 9), the total data length may be 4105 bits. The total data length of 4105 bits may include 4096 bits of the data block to be read, a start bit, an end bit, and 7 cyclic redundancy check (CRC) bits.
FIG. 5(b) illustrates another conventional data block transmission structure. With the above described assumptions, referring to FIG. 5(b), a bus may use data lines DAT3, DAT2, DAT1, and DAT0 to achieve a total data length of 1033 bits for the given data block. The difference (e.g., between the total data lengths of the conventional data block transmission structures of FIG. 5(a) and FIG. 5(b)) may affect a read latency (e.g., a time between a read request and a completion of the sending of the requested read data). For example, if one bit is read per clock cycle using a conventional 25 MHz clock oscillator, data transmission may take 164 nanoseconds (ns) (e.g., as in FIG. 5(a)). In another example, when using the bus with data lines DAT3, DAT2, DAT1 and DATA0, as illustrated in FIG. 5(b), data transmission may take 1 ns (e.g., as in FIG. 5(b).
In another example, assuming the conventional 25 MHz clock oscillator may be used to read a data block of 1 megabyte (Mbyte), a lower limit for the data transmission speed may be 0.32 seconds when using the single data line of FIG. 5(a) and the lower limit may be 0.08 seconds when using the bus of FIG. 5(b). Further, the transmission time may be further increased by the command and response through the command line. Therefore, the memory card 100 may not be used for conventional applications where data may be required to be read or written with a latency less than a given threshold (e.g., 0.08 seconds). Further, while increasing a number of data lines may decrease the latency for a memory device (e.g., memory card 100), it may be difficult to increase the number of data lines while also satisfying other desired system requirements, such as reducing a size of the memory device.